Building High-Performance RISC-V Cores for Everything



Building High-Performance RISC-V Cores for Everything

Building High-Performance RISC-V Cores for Everything

Wei-han Lien is Tenstorrent’s Chief RISC-V Architect, and he’s been lead designer on chips like Apple’s M1. Now he heads up a team building the highest-performance RISC-V cores on the market. Here’s why RISC-V is important.

[00:00] x86 vs Arm vs RISC-V
[00:47] RISC-V initial targets
[02:43] Jim part 1
[03:13] Building a CPU Core
[04:34] Tenstorrent’s Hardware
[05:48] Wei-han Lien: Arm vs RISC-V
[07:37] Wei-han Lien: 8-wide RISC-V
[09:07] Wei-han Lien: Training vs Inference
[10:10] Tenstorrent’s Ascalon…
[11:06] Derivatives for Laptop
[11:31] Wei-han Lien: Chiplets
[13:09] Jim Keller: https://www.youtube.com/watch?v=YOiXomG9FhE
[17:46] High Performance at 128 cores!

https://tenstorrent.com/

The full Wei-han interview will be uploaded soon!
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